Wireless communications have become extremely popular in these years. In particular, even if initially conceived for simply enabling voice communications, wireless communication systems are evolving toward the offering of multimedia services with high data-rate.
From this viewpoint, high speed processing is required in order to support wide-band communications.
Moreover, the trend in wireless communications is toward (mobile) terminals that are able to support multiple standards, such as for example the coexistence of the IEEE 802.11 standard (Wireless LAN or WLAN) and the Wideband CDMA (the standard adopted for 3G cellular networks, like UMTS networks), and emerging variation thereof.
In other words, it would be highly desirable that the processors exploited in devices used in the wireless communication systems have an architecture such as to be able to perform different algorithms, depending on the adopted standard: this would increase their flexibility.
In this context, it has been observed that known approaches such ASIC (acronym for Application Specific Integrated Circuit) and DSP (acronym for Digital Signal Processor) data processor circuits have a number of limitations.
In fact, each of above mentioned solutions satisfies only one among the high-speed processing and flexibility requirements.
The ASICs feature good performance in terms of throughput, but they consist of a dedicated hardware. Thus, they are not adapted to being modified for tracking the rapid modifications of the wireless communications technology. In particular, a new dedicated hardware, i.e. the existing ASIC has to be heavily modified or a new ASIC has to be designed whenever new, emerging requirements appears.
On the other side, even more recent DSPs, although they are highly flexible, they are designed for a general purpose use, and hence are still not capable to sustain the high data rates needed in wireless communications.
It should be noted that the trade-off between high-speed processing and flexibility also depends on the higher or lower level (“granularity”) of the instructions which the processor is able to perform. In particular, the instructions having a “thick granularity” allow executing complex operations (e.g., Fast Fourier Transform—FFT) which are however specific of a certain application and hardly re-usable in different contexts, whereas the instructions having a “fine granularity”, that allow executing ordinary, relatively low-level operations (e.g., additions and the like), are more flexible and re-usable in different contexts, but are not optimized for performing complex operations. In this context, an ASIC can be seen as a particular processor capable of performing a unique, fixed instruction, customized for the specific application the ASIC is designed for, thus limiting the possibility of being re-used for different applications; in other words, an ASIC is custom-designed in view of a well defined, specific application, and is optimized for that application only. On the contrary, a DSP is adapted to perform a large collection of general-purpose fine-granularity instructions, without being specifically optimized for performing any complex operation, so it is not adapted for wireless communication applications, due to the relatively low processing speed.